The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices requires submicron design features, high reliability and increased manufacturing throughput for competitiveness. Conventional practices are primarily based upon a silicon gate CMOS process wherein a gate electrode and corresponding source and drain regions formed by self alignment, and the withstand voltage (threshold voltage) determined by the impurity concentration level of the drain region.
Conventional practices also comprise forming, on a single chip, both low voltage transistors in internal logic circuitry for miniaturization and high-speed operation and high voltage transistors input/output (I/O) circuits for interface with exterior devices. Conventionally, the high voltage transistors are obtained by providing a low diffusion density in the drain region, the low voltage transistors are obtained by providing a high diffusion density in the drain region.
Transistors in I/O circuitry structure require gate oxide layers of a relatively high thickness, e.g., to withstand a relatively high voltage, such as about 7-8 volts for electrostatic discharge protection. However, due to miniaturization, the gate oxide layers of transistors in the logic core region are reduced in thickness below that necessary for optimum I/O gate oxide performance. In other words, the drive to increase density requires production worthy techniques for forming transistors having differential gate oxide thicknesses on a single chip.
Techniques for obtaining the high and low voltage transistors on a single chip are described in U.S. Pat. No. 5,254,487 and U.S. Pat. No. 5,047,358. However, such methodologies are complex as requiring plural masking and implanting steps in addition to implanting steps to adjust the threshold voltage of low voltage transistors and high voltage transistors.
There is a need for simplified, efficient and production worthy methodology enabling the formation of both high voltage CMOS and low voltage CMOS transistors on a single chip.